FPGA Implementation of FIR Filter using Various Algorithms: A Retrospective

Download Full Text
Author(s):
Jinalkumari K. Dhobi, Dr. Y. B. Shukla,  Dr. K.R. Bhatt
Published Date:
March 05, 2014
Issue:
Volume 4, Issue 2
Page(s):
19 - 24
DOI:
10.7815/ijorcs.42.2014.081
Views:
7175
Downloads:
111

Keywords:
da, da-obc, cse, sopot, fpga
Citation:
Jinalkumari K. Dhobi, Dr. Y. B. Shukla,  Dr. K.R. Bhatt, "FPGA Implementation of FIR Filter using Various Algorithms: A Retrospective". International Journal of Research in Computer Science, 4 (2): pp. 19-24, March 2014. doi:10.7815/ijorcs.42.2014.081 Other Formats

Abstract

This Paper is a review study of FPGA implementation of Finite Impulse response (FIR) with low cost and high performance. The key observation of this paper is an elaborate analysis about hardware implementations of FIR filters using different algorithm i.e., Distributed Arithmetic (DA), DA-Offset Binary Coding (DA-OBC), Common Sub-expression Elimination (CSE) and sum-of-power-of-two (SOPOT) with less resources and without affecting the performance of the original FIR Filter.

  1. Steven W. Smith, “The Scientist and Engineer’s Guide to Digital Signal Processing”. California Technical Publishing San Diego, California, Second Edition 1999.
  2. Wang, Wei, Swamy, M.N.S., Ahmad, M.O., "Low power FIR filter FPGA implementation based on distributed arithmetic and residue number system" Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on, vol.1, no., pp.102, 105 vol.1, 2001. doi: 10.1109/MWSCAS.2001.986125
  3. Saurabh Singh Rajput, Dr.S.S.Bhadauria, “Implementation of Fir Filter Using Efficient Window Function and Its Application in Filtering a Speech Signal” International Journal of Electronics and Mechanical Controls, Volume 1 Issue 1 November 2012.
  4. Sen M. Kuo, Bob. H. Lee and Wenshun Tian, “Real-Time Digital Signal Processing Implementations and Applications” John Wiley & Sons, Ltd, England, Second Edition 2006.
  5. Sonika Gupta, Aman Panghal, “Performance Analysis of FIR Filter Design by Using Rectangular, Hanning and Hamming Windows Method,” International Journal of Advanced Research in Computer Science and Software Engineering, Volume 2, Issue 6, June 2012.
  6. Gao Jinding, Hou Yubao, Su Long, "Design and FPGA Implementation of Linear FIR Low-pass Filter Based on Kaiser Window Function" Intelligent Computation Technology and Automation (ICICTA), 2011 International Conference on , vol.2, no., pp.496,498, 28-29 March 2011. doi: 10.1109/ICICTA.2011.408
  7. Croisier, D.J.Esteban, M.E.Levilion, V.Rizo, "Digital Filter for PCM Encoded Signals" U.S.Patent, No.3, 777, 130, 1973.
  8. A. Peled and B. Liu, “A new hardware realization of digital filters” IEEE Transactions on A.S.S.P., vol. ASSP-22, pp. 456–462, December 1974.
  9. Bo Hong, Haibin Yin, Xiumin Wang, Ying Xiao, "Implementation of FIR filter on FPGA using DA-OBC algorithm" Information Science and Engineering (ICISE), 2010 2nd International Conference on , vol., no., pp.3761,3764, 4-6 Dec. 2010.
  10. M. Thenmozhi, N. Kirthika, "Analysis of Efficient Architectures for FIR filters using Common Subexpression Elimination Algorithm,” International Journal of Scientific & Technology Research Volume 1, Issue 4, May 2012.
  11. Damian, C. Lunca, E., "A low area FIR filter for FPGA implementation" Telecommunications and Signal Processing (TSP), 2011 34th International Conference on, vol., no., pp.521, 524, 18-20 Aug. 2011.
  12. Heejong Yoo, David V.anderson, "Hardware-efficient distributed arithmetic architecture for high-order digital filters" in proc. IEEE International conference on Acoustics, speech, and signal processing(ICASSP’05),Vol.5, pp.125-128 2005.
  13. Mahesh, R. Vinod, A.P., "A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters" Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.27, no.2, pp.217,229, Feb. 2008.
  14. John G. Proakis., Dimitris G. Manokalis, “Digital Signal Processing Principle algorithms and applications” PHI publication, New Jersey, Third Edition 2004.
  15. Catalin Damian, Cristian Zet, Cristian Fosalau, Mihai Cretu, “Real, Reactive and Apparent Power Computing Using FPGA and PWM Intermediary Conversion” XX IMEKO TC4, Florence, Italy, Sept. 2008.
  16. K. S. Yeung, S. C. Chan, “Multiplier-Less Digital Filters Using Programmable Sum-Of-Power-Of-Two (Sopot) Coefficients” IEEE International Conference on Field Programmable Technology, 78 – 84, 16-18 Dec. 2002.

  • Bailey III, John Phillip. Digital Reverse Time Chaos and Matched Filter Decoding. Diss. Auburn University, 2015.