FPGA Implementation of FIR Filter using Various Algorithms: A Retrospective

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Jinalkumari K. Dhobi, Dr. Y. B. Shukla,  Dr. K.R. Bhatt
Published Date:
March 05, 2014
Volume 4, Issue 2
19 - 24

da, da-obc, cse, sopot, fpga
Jinalkumari K. Dhobi, Dr. Y. B. Shukla,  Dr. K.R. Bhatt, "FPGA Implementation of FIR Filter using Various Algorithms: A Retrospective". International Journal of Research in Computer Science, 4 (2): pp. 19-24, March 2014. doi:10.7815/ijorcs.42.2014.081 Other Formats


This Paper is a review study of FPGA implementation of Finite Impulse response (FIR) with low cost and high performance. The key observation of this paper is an elaborate analysis about hardware implementations of FIR filters using different algorithm i.e., Distributed Arithmetic (DA), DA-Offset Binary Coding (DA-OBC), Common Sub-expression Elimination (CSE) and sum-of-power-of-two (SOPOT) with less resources and without affecting the performance of the original FIR Filter.

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